Interconnect and delay testing with a 4800-pin board tester

INTERCONNECT AND DELAY TESTING WITH A 4800-PIN BOARD TESTER Shuichi Kameyama", Hideyuki Ohara**, Chihiro Endo***, and Naoki Takayamat Fujitsu Limited, Kawasaki, Japan *Production Technology Development Department **Circuit Technology Department ***DA Development Department 'Fujitsu Computer Technology Limited, Yokohama, Japan It i s difficult to test today's highly complex, high-pincount and high-speed VLSI boards using conventional test methods such as in-circuit or functional testing. To overcome this problem, we developed a 4,800-pin board tester implementing two new test methodologies, Net Test and Board Delay Test. The Net Test verifies interconnections on boards without using a bed-of-nails or the Boundary Scan technique. The Board Delay Test checks a boards operation at the system clock rate. This paper describes the test methodologies and the board tester.