Architectural Synthesis with Interconnection Cost Control

Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper.

[1]  XuMin,et al.  Layout-driven RTL binding techniques for high-level synthesis using accurate estimators , 1997 .

[2]  Atila Alvandpour,et al.  A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction , 1997 .

[3]  Olivier Sentieys,et al.  GAUT: An architectural synthesis tool for dedicated signal processors , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[4]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[5]  Keikichi Tamaru,et al.  A Floorplan Based Methodology for Data-Path Synthesis of Sub-micron ASICs , 1996 .

[6]  W.W.-M. Dai.  Chip Parasitic Extraction And Signal Integrity Verification , 1997, Proceedings of the 34th Design Automation Conference.

[7]  Syed A. Rizvi.  Analyzing the tolerance and controls on critical dimensions and overlays as prescribed by the National Technology Roadmap for Semiconductors , 1997, Other Conferences.

[8]  Zebo Peng,et al.  Estimation and consideration of interconnection delays during high-level synthesis , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[9]  Francisco Tirado,et al.  A method for area estimation of data-path in high level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Werner Grass.  A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraints , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[11]  Román Hermida,et al.  Heuristics for branch-and-bound global allocation , 1992, EURO-DAC '92.

[12]  Emmanuel Casseau,et al.  Architectural Synthesis of a Complex Application : the Viterbi Algorithm , 1999 .

[13]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[14]  Keikichi Tamaru,et al.  Effects of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study , 1997 .