A generalized extraction system for VLSI

A generalized extraction system (GES) performs verification of circuits through logic extraction from transistor/component netlists, identification and location of logic errors within and between components, pin-to-pin critical path analysis, and generation of VHDL and ML. Extraction rules are automatically built from structural VHDL code. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders, 32-bit registers, and ALUs.<<ETX>>