Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordlengths avoiding time and power consuming reconfiguration. The new data-path can operate in SIMD fashion and guarantees high parallelism levels when operations on lower precisions are executed. It also supports IEEE-754 compliant single precision floating-point addition and multiplication. The proposed circuit has been characterized using VIRTEXII XILINX devices, but it can be efficiently used also in other FPGA families.

[1]  E. L. Harder,et al.  The Institute of Electrical and Electronics Engineers, Inc. , 2019, 2019 IEEE International Conference on Software Architecture Companion (ICSA-C).

[2]  Kunle Olukotun,et al.  REMARC (abstract): reconfigurable multimedia array coprocessor , 1998, FPGA '98.

[3]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[4]  Bede Liu,et al.  Understanding multimedia application characteristics for designing programmable media processors , 1998, Electronic Imaging.

[5]  Joseph J. F. Cavanagh Digital Computer Arithmetic: Design And Implementation , 1984 .

[6]  Stamatis Vassiliadis,et al.  Coarse reconfigurable multimedia unit extension , 2001, Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing.

[7]  Borko Furht,et al.  Processor Architectures for Multimedia , 1998 .

[8]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[9]  Marco Lanuzza,et al.  Variable precision arithmetic circuits for FPGA-based multimedia processors , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Guido D. Salvucci,et al.  Ieee standard for binary floating-point arithmetic , 1985 .

[11]  Brent E. Nelson,et al.  Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture , 2002, FPL.

[12]  Ansi Ieee,et al.  IEEE Standard for Binary Floating Point Arithmetic , 1985 .

[13]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[14]  Rudy Lauwereins,et al.  Low Power Coarse-Grained Reconfigurable Instruction Set Processor , 2003, FPL.

[15]  Diederik Verkest,et al.  A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs , 2004, Microprocess. Microsystems.

[16]  S. McBader,et al.  A programmable image signal processing architecture for embedded vision systems , 2002, 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628).