An Efficient Two-Dimension BIST Compression Approach

In this paper a two-dimension BIST compression scheme is presented; the proposed scheme is utilized in order to drive down the number of deterministic vectors to achieve complete fault coverage in BIST applications. By introducing shifting compression and input reduction, vertical and horizontal compression are realized respectively to achieve two-dimension BIST compression. Experimental results show that the BIST shifting compression based on input reduction can achieve great compression rate as much as 99%. Comparisons with previously competitive presented schemes indicate that the proposed scheme provide an efficient BIST compression approach with lower storage overhead.

[1]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[3]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[4]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[5]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[6]  Tony Ambler,et al.  Economics of Built-in Self-Test , 2001, IEEE Des. Test Comput..

[7]  M. H. Bindu,et al.  Accumulator-Based-3 Weight Pattern Generation , 2015 .

[8]  Sandeep K. Gupta,et al.  Efficient BIST TPG design and test set compaction via input reduction , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[10]  Seongrnoon Wang,et al.  Low hardware overhead scan based 3-weight weighted random BIST , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Huaguo Liang,et al.  A mixed mode BIST scheme based on reseeding of folding counters , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[12]  Sandeep K. Gupta,et al.  A methodology to design efficient BIST test pattern generators , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[13]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[14]  Sandeep K. Gupta,et al.  Test generation and embedding for built-in self-test , 1996 .