Noise-Coupled Delta-Sigma ADCS

This chapter describes wideband discrete-time DS ADCs with high linearity. Noise coupling is introduced in a modulator (self coupling) or between two split modulators (cross coupling) to get an improved noise shaping performance. Time-interleaving further enhances the noise shaping of the cross-coupled split modulators. Several prototype design examples are provided to demonstrate the effectiveness of the proposed technique.

[1]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[3]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[4]  Apparajan Ganesan,et al.  Theory and practical implementation of a fifth-order sigma-delta A/D converter , 1991 .

[5]  M.H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[6]  Gabor C. Temes,et al.  Improved low-distortion ΔΣ ADC topology , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[7]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR , 2008, IEEE Journal of Solid-State Circuits.

[8]  Andreas Kaiser,et al.  Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.

[9]  Gabor C. Temes,et al.  Enhanced split-architecture delta-sigma ADC , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[10]  Sudhakar Pamarti A Theoretical Study of the Quantization Noise in Split Delta–Sigma ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  F. Maloberti,et al.  A 14mW Multi-bit /spl Delta//spl Sigma/ Modulator with 82dB SNR and 86dB DR for ADSL2+ , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[12]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[13]  K.C.-H. Chao,et al.  A higher order topology for interpolative modulators for oversampling A/D converters , 1990 .

[14]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 2000 .

[15]  Koichi Hamashita,et al.  Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC , 2010, IEEE Journal of Solid-State Circuits.

[16]  Michael M. Miyamoto,et al.  A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique , 2006, IEEE Custom Integrated Circuits Conference 2006.

[17]  Gabor C. Temes,et al.  An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD , 2009, IEEE J. Solid State Circuits.

[18]  Richard Schreier,et al.  An empirical study of high-order single-bit delta-sigma modulators , 1993 .

[19]  Gabor C. Temes,et al.  Noise-Coupled Multi-Cell Delta-Sigma ADCs , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[20]  Thomas Burger,et al.  A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  F. Maloberti,et al.  A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications , 2007, IEEE Journal of Solid-State Circuits.

[22]  Paul R. Gray,et al.  An 8b 85MS/s Parallel Pipeline A/D Converter in 1μm CMOS (Special Section on the 1992 VLSI Circuits Symposium) , 1993 .

[23]  M. Clara,et al.  A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution , 2004, IEEE Journal of Solid-State Circuits.

[24]  Gil-Cho Ahn,et al.  A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR , 2005, VLSIC 2005.

[25]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[26]  Gabor C. Temes,et al.  A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[27]  F. Kuttner,et al.  A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[28]  Richard Schreier,et al.  Stability tests for single-bit sigma-delta modulators with second-order FIR noise transfer functions , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[29]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[30]  Kenneth W. Martin,et al.  High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[31]  Lars Risbo Stability predictions for high-order /spl Sigma//spl Delta/ modulators based on quasilinear modeling , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[32]  Mohamed Dessouky,et al.  Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping , 2001 .

[33]  Gabor C. Temes,et al.  Noise-coupled /spl Delta//spl Sigma/ ADC's , 2006 .

[34]  Michael M. Miyamoto,et al.  An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[35]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[36]  I. Mehr,et al.  A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[37]  Paul R. Gray,et al.  An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS , 1993 .

[38]  P. Hurst,et al.  A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.

[39]  Gabor C. Temes,et al.  Enhanced split-architecture /spl Delta/-/spl Sigma/ ADC , 2006 .

[40]  I. Galton,et al.  An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).