Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current

Active gate driving, where the gate signal is actively profiled, has been shown to reduce EMI, overshoot, and switching loss, in silicon power converters. Recently, much faster gate drivers with the ability to profile at a 100 ps resolution have been reported, which has opened up the possibility of actively driving emerging wide-bandgap devices. This could allow Gallium Nitride (GaN) and Silicon Carbide (SiC) FETs to be switched faster than is currently possible, as unwanted switching features such as current ringing at turn-on could be eliminated. However, these drivers have previously only been demonstrated with pre-programmed gate profiles that have been optimized at certain operating conditions, whereas converters typically operate in a range of conditions. In this paper, some limitations of using fixed gate profiles on GaN FETs are reported for the first time, and a new method of profile adaptation is demonstrated. First, the gate profiles in a 400 V GaN bridge-leg are optimized to minimize current ringing at turn-on for a given load current. Then, the load current is varied, showing that the gate signal profile remains close to optimal for ±20% changes in current. Also, over a larger range of at least ±35%, the profiled waveform performs better than a non-profiled gate waveform. It is then demonstrated that by slightly reducing the driver's internal clock frequency with increasing load current, the profile is re-optimized for new load currents. It is concluded that driver clock frequency adaptation may be a means of adapting gate profiles to load current variation and possibly also to temperature variation.