On the Architectural Design of Frequency-Agile Multi-Standard Wireless Receivers

A flexible, reconfigurable receiver architecture that extends the direct conversion architecture is presented. The receiver structure is based on high dynamic range/lowpower Σ∆ analog-to-digital converters (ADC) and digital signal processing functions implemented locally on the radio frequency integrated circuit (RFIC). This relaxes requirements for the analog part of the receiver and enables configurable receive-bandwidths, because channel filtering is realized in the digital domain. Since analog building blocks have limited reconfiguration capabilities by nature of their implementation, the extension of the conventional analog signal processing blocks by a digital front-end (DFE) greatly enhances the flexibility of the RFIC. Key building blocks for the proposed receiver, such as tunable RF filters, ADC and DFE building blocks are discussed.

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