A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average phase error. The power consumption is 15mW for 1V supply.

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