Simulating Building Blocks for Spikes Signals Processing

In this paper we will explain in depth how we have used Simulink with the addition of Xilinx System Generation to design a simulation framework for testing and analyzing neuro-inspired elements for spikes rate coded signals processing. Those elements have been designed as building blocks, which represent spikes processing primitives, combining them we have designed more complex blocks, which behaves like analog frequency filter using digital circuits. This kind of computation performs a massively parallel processing without complex hardware units. Spikes processing building blocks have been written in VHDL to be implemented for FPGA. Xilinx System Generator allows co-simulating VHDL entities together with Simulink components, providing an easy interface for presented building block simulations and analysis.

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