Implementation of RSA Algorithm Using SOPC Technology

In a highly connected world, security in networks is still a significant challenge for researchers. However, cryptographic algorithms are computationally intensive and a number of security schemes have recently emerged intended to overcome the limit processing and power resource. The processors used in Field Programmable Gate Array (FPGA) embedded systems are known to have a modest performance. This paper presents an innovative system-on-a-programmable-chip (SOPC) based approach for the Rivest-Shamir-Adleman (RSA) algorithms evaluation which is implemented on an Altera Cyclone II FPGA. As compared to traditional customize processor design, the proposed implementation of the RSA processor is believed to be low cost, more flexible.