A high performance low power dynamic PLA with conditional evaluation scheme

This paper proposes a high performance and low power dynamic CMOS PLA that minimizes active power consumption. The proposed PLA uses a conditional evaluation scheme to reduce short circuit power consumption during the evaluation phase. The proposed PLA reduces delay by 13.8%, dynamic power by 46%, and total power delay product (PDP) by 53.4% compared to the conventional clock-delayed PLA in a 0.25 /spl mu/m CMOS process technology.