A system for critical path analysis based on back annotation and distributed interconnect impedance models

This paper describes a VLSI CAD system that automatically selects optimal interconnect impedance models and embeds them into circuit simulation files each identified as a critical worst case timing path. The CAD system initially identifies pre-layout critical timing paths and back annotates these paths with post-layout interconnect impedances. Accurate post-layout resistive and capacitive interconnect impedances are automatically extracted, their magnitudes are compared to the path specific device dependent RC loads of each cell-to-cell node, and an approapriate RC lumped model is selected to optimally model the distributed nature of the RC interconnect impedance of that particular cell-to-cell node. These inter-connect RC impedance models are then back annotated into a SPICE formatted circuit simulation file for the precise determination of the timing behaviour of these critical paths. Therefore, timing accuracy and CPU efficiency are optimised on a node by node basis. This analysis system is tailored to support high performance circuits while maintaining automated layout database independence and maximal design flexibility.