Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

This paper presents a novel design of a 12-bit multi-channel single-ramp analog-to-digital converter (ADC) for imaging detector systems. To overcome the problem of long conversion time in the classic Wilkinson ADC, a new architecture using a counter and delay line interpolations is proposed. Two 5-bit Gray counters are designed for the coarse conversion. The time interpolation using an array of five delay-locked loops (DLLs) and the multiphase sampling technique are proposed for the fine conversion. The 140-phase delay clocks are generated by the array and pseudo 7-bit fine resolution is achieved. A one-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The total conversion time is about 400 ns, which corresponds to a sampling rate of 2.5 MS/s. The proposed ADC can be utilized in many fields, such as high-energy physics, biomedical imaging, and space applications.

[1]  Hanjun Jiang,et al.  High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy , 2009, IEEE Transactions on Instrumentation and Measurement.

[2]  Christine Hu-Guo,et al.  A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors , 2009, 2009 IEEE International Workshop on Imaging Systems and Techniques.

[3]  Majid Ahmadi,et al.  A Delay Generation Technique for Narrow Time Interval Measurement , 2009, IEEE Transactions on Instrumentation and Measurement.

[4]  W. Gao,et al.  Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging , 2010, IEEE Transactions on Nuclear Science.

[5]  S.P. Voinigescu,et al.  A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees , 2009, IEEE Journal of Solid-State Circuits.

[6]  F. Borghetti,et al.  A Complete Read-Out Channel With Embedded Wilkinson A/D Converter for X-Ray Spectrometry , 2007, IEEE Transactions on Nuclear Science.

[7]  Gunhee Han,et al.  A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs , 2009 .

[8]  S. Gambini,et al.  Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[9]  D. Brasse,et al.  Design of a High Performances Small Animal PET System With Axial Oriented Crystals and DOI Capability , 2009, IEEE Transactions on Nuclear Science.

[10]  J.. Bouvier,et al.  A Low Power and Low Signal 5-bit 25 MS/s Pipelined ADC for Monolithic Active Pixel Sensors , 2007, IEEE Transactions on Nuclear Science.

[11]  J. Christiansen,et al.  An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[12]  Helmuth Spieler,et al.  Imaging detectors and electronics - A view of the future , 2004 .

[13]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[14]  E. Delagnes,et al.  A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock , 2007, IEEE Transactions on Nuclear Science.

[15]  L. G. Clonts,et al.  A multi-channel ADC for use in the PHENIX detector , 1996, 1996 IEEE Nuclear Science Symposium. Conference Record.