Debugging synthesizeable VHDL Programs

This paper describes the use of model-based diagnosis for locating bugs in hardware designs. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesizeable (register transfer level) programs. This are programs which can be automatically converted into a gate level description without changing their behavior. Therefore almost all VHDL programs are elements of this subset. We show the conversion of VHDL programs into a logical representation. Take this representation and apply model-based diagnosis. The resulting diagnoses are mapped back to the VHDL code fragments of the original program explaining misbehaviors. Finally, we specify some rules optimizing the obtained results. We further present some arguments showing that the proposed debugging technique scales up to large designs.