A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS

A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200–400 mV pp signals at date rates of 1.25–5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm2, while the actual driver occupies only 190 μm2. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44–1.4 mW/Gbps with external clock and 2.6–4.7 mW/Gbps with clock synthesizer.

[1]  R. Mooney,et al.  A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[2]  Thomas Toifl,et al.  A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$16 dB Return Loss Over 10 GHz Bandwidth , 2008, IEEE Journal of Solid-State Circuits.

[3]  Markku Rouvala,et al.  Multi-gigabit serial link emissions and mobile terminal antenna interference , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[4]  A.P. Chandrakasan,et al.  Minimum Energy Tracking Loop With Embedded DC–DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[5]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[6]  Lei Luo,et al.  A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[7]  Samuel Palermo,et al.  A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Martin L. Schmatz,et al.  Jitter measurements of high-speed serial links , 2004, IEEE Design & Test of Computers.

[9]  M. Horowitz,et al.  A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[10]  Amr Elshazly,et al.  A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Olli Viitala,et al.  A Scalable Low-Voltage Signaling (SLVS) Driver for a Low-Power MIPI M-PHY Serial Link in 40 nm CMOS , 2012 .

[12]  James E. Jaussi,et al.  A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[13]  J. Silva-Martinez,et al.  Low-voltage low-power LVDS drivers , 2005, IEEE Journal of Solid-State Circuits.

[14]  Goichi Ono,et al.  A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process , 2010, IEEE Journal of Solid-State Circuits.

[15]  Woo-Young Choi,et al.  A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology , 2011, 2011 International SoC Design Conference.

[16]  Davide De Caro,et al.  A novel high-speed sense-amplifier-based flip-flop , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Byungsub Kim,et al.  A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[18]  Chih-Kong Ken Yang,et al.  Power analysis for high-speed I/O transmitters , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).