Fault Tolerant Arithmetic Logic Unit

Low power design is most challenging in this era of IC technology and shaken the Moore’s law. Various techniques have been invented for low power design and researchers are taking lot of pain to investigate new steps and methods to achieve low power goal. Reversible logic is seeking attention from last one decade and can be employed to balance between power and performance. Reversible logic is based on principle of no bit loss and claims almost no power dissipation. Although paradigm shifts from conventional logic to reversible logic is tedious but there is no other way looking around to reduce power dissipation. Many Reversible logic based arithmetic and logic units are available in literature but incorporating fault tolerance is demand of various applications. This paper aims in designing fault tolerant arithmetic logic unit based on high functionality conservative and parity preserving logic based gates. The quantum cost of used gates in proposed design is verified using RCViewer+ tool and performance of proposed design is evaluated with respect to existing designs in literature.