Design of high-speed driving circuit for large area array full frame transfer CCD

With the rapid development of the aerospace camera and remote sensing application technologies, CCDs, as a photoelectric sensor, have evolved from line array toward area array CCDs especially large area array CCDs which can realize a broader coverage and avoid the technical difficulties from jointing multiple small area array CCDs in addition to improving resolution. Large area array full-frame transfer CCDs are introduced in the dissertation with focuses on the driving time sequence and working modes. Large area array CCDs, due to the great number of pixels, requires intensive driving power and a readout rate up to 20MHz, which cannot be met by the driving circuit of ordinary line array CCDs. So, time sequence signals generated by FPGA are amplified by a high power MOS driver to meet the driving demand of large area array CCDs. Moreover, traditional driving circuit is improved according to the driving signal waveform theory, thus the output quality of CCD analog signals is enhanced. Large area array CCD's output features high resistance and high DC level. In order to improve the load capacity and anti-interference capability of the output signals, operational amplifiers, selected based on the working voltage and signal bandwidth of the output signals, are applied as the buffer. The correctness of the design is verified through software simulations and circuit tests. According to the test results, the high-speed driving circuit can satisfy the application in large area array CCDs with a readout rate up to 20MHz and good quality of simulation signals.