Structured analysis and VHDL in embedded ASIC design and verification

With current VLSI technology it is possible to integrate complex systems in a single chip. Therefore much more efficient design and verification methods are needed especially at system level. The authors are using real-time structured analysis/structured design in logical behaviour specification and design of systems. They have developed automatic transformation from this graphical analysis and specification method to VHDL-hardware description language. The resulting code can be simulated and so the behaviour of system can be verified at an early design phase. This paper presents the transformation principles and also describes the whole design process of ASICs.<<ETX>>