Design and Implementation of a Pipelined ADC for Silicon Microstrip Detector Readout Circuit

This paper describes a 12-bit 80 MS/s pipelined analog-to-digital converter (ADC) for silicon microstrip detector readout circuit implemented in SMIC 0.13$\mu$m CMOS process. The ADC adopts an opamp-sharing Multiplying Digital-to-Analog Converter (MDAC) with dual-input op-amp to suppress the memory effect. With the proposed clock, the kickback noise of dynamic comparator has no influence on sampling signal. And there is no crosstalk path in the two successive stages. The simulation result shows that the signal-to-noise-plus-distortion (SNDR) is 71.7 dB, the spurious free dynamic range (SFDR) is 85 dB, the total harmonic distortion (THD) is -S1.7 dB, and the effective number of bits (ENOB) is 11.61 bit with the input at 1 MHz.

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