FPGA Based Attitude Control System Architecture for Increased Performance

For micro-satellites the required attitude accuracy, agility and autonomy along with desired parallel processing of payload images in real-time needs to be achieved within limited power and computational resources. Providing fast, parallel execution while still small in hardware size and modest in power consumption field programmable gate array (FPGA) based on-board computers (OBC) have the potential to highly increase system performance. The Flying Laptop is a micro-satellite currently under development at the Institute of Space Systems, Universitat Stuttgart. The attitude control system together with the on-board navigation system is implemented as hardware in an FPGA. The architecture including the sensors, actuators and control algorithms are described in this paper. urable computers using FPGAs have been conducted due to the risk of non-radiation susceptibility. One of them being the Adaptive Instrument Module3 of the Australian micro-satellite Fedsat which was developed for in-orbit evaluation of RAM-based FPGAs. A micro-satellite typically has limited power and computational resources. In order to achieve the required agility, accuracy of the navigation & attitude control system and autonomy along with the parallel processing of the payload images in real-time, for the Flying Laptop the decision was made to use an FPGA based onboard computer (OBC). ACS HARDWARE The satellite motion is monitored by five different types of sensors: two three-axis magnetometers, two coarse sun sensors, four fiber-optic rate sensors, one autonomous star tracker with two camera heads and three GPS receivers. The actuators that rotate the satellite to the desired attitude are four reaction wheels and three magnetic torquers. All sensors and actuators are connected to the FPGA in a star like configuration, increasing the system reliability by using separate RS-422 ports, digital I/O lines, I2C buses and an IBIS bus. All connections of the ACS hardware devices to the FPGA on-board computer are displayed in Figure 2.