Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

In this paper we propose a methodology that takes into account bit-width to optimize area and power consumption of hardware architectures provided by high-level synthesis tools. The methodology is based on a bit-width analysis using information that comes from the designer. This bit-width information is propagated through a graph which models the application. The resulting annotated graph enables datapaph structure optimizations for high-level synthesis without increasing dramatically its processing time (complexity: O(n)). The methodology results in an area reduction from 17% to 43% for on a Sum of Absolute Difference (SAD) computation used in block matching algorithms. The proposed approach can also be applied in a more general design context for sizing the data of an application knowing the input data formats.

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