A TDC Enabler Based on DFF Chain for Low Power TDC System

Time-to-digital converter(TDC)was a key block in an all-digital phase-locked loop(ADPLL),with its power consumption being one of the major parts of the power consumption of the whole ADPLL system.A TDC enabler based on DFF chain whose function would not be affected by metastability was proposed for the TDC based on two pseudo-differential inverter-delay chains.Some modifications to the architecture of the TDC were done to reduce the power consumption of the TDC system.The circuit was designed and simulated in the SMIC 0.18μm CMOS process.The simulation results showed that the power consumption of the TDC system could be reduced by more than 74%.