Timing analysis of transistor stack for leakage power saving

In low-voltage and low-Vt CMOS circuits, transistor stack effect can be used to control the leakage power dissipation. But it may lead to performance loss and larger dynamic power. In this paper, we analyze the relation between performance loss and leakage power dissipation saving when transistor stack is inserted. The variations of all kinds of timing parameters versus the number of transistors in the stack are demonstrated. Two kinds of stack architecture: NMOS and P-NMOS stack architectures are respectively simulated. The optimized number applied to different stack architecture is presented. How to use stack effect in leakage saving is classified and the strategy is also discussed in this paper. Furthermore, the comparison between NMOS and P-NMOS stack architecture is shown, which is helpful for designers make a choice.

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