An on-chip para-C calibration architecture for successive approximation ADC

Power consumption becomes an increasingly critical issue for modern CMOS imaging sensors. To minimize the power consumption, metal-oxide-metal (MOM) capacitors are generally used in SAR ADCs. In these ADCs, the parasitic capacitance from routing metals affect significantly to the ADC linearity. In this paper, this effect is analyzed systematically. This paper also introduces the design of a new on-chip calibration technique to compensate the parasitic capacitance robustly. The design is implemented in silicon using a 65nm CMOS process. Simulation shows that the designed 3.125MS/s 12bit SAR ADC can achieve 10.8bit ENOB (effective number of bits) reliably with this para-C calibration technique with a significant variation of the routing parasitics. Before calibration, the ADC achieves 8.7bit ENOB, which is mainly due to the poor linearity. With proper split of the capacitor array, the technique needs little calibration overhead.