27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals

Applications like spectrum sensing, radar signal processing, and pattern matching by convolving a signal with a long code, as in GPS, require large FFT sizes. ASIC implementations of such FFTs are challenging due to their large silicon area and high power consumption. However, the signals in these applications are sparse, i.e., the energy at the output of the FFT/IFFT is concentrated at a limited number of frequencies and with zero/negligible energy at most frequencies. Recent advances in signal processing have shown that, for such sparse signals, a new algorithm called the sparse FFT (sFFT) can compute the Fourier transform more efficiently than traditional FFTs [1].

[1]  David Blaauw,et al.  A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  Piotr Indyk,et al.  Simple and practical algorithm for sparse Fourier transform , 2012, SODA.

[3]  Chen-Yi Lee,et al.  A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems , 2008, IEEE Journal of Solid-State Circuits.

[4]  A.N. Willson,et al.  A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring , 2006, IEEE Journal of Solid-State Circuits.

[5]  Dejan Markovic,et al.  Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example , 2012, IEEE Journal of Solid-State Circuits.