Using BIST control for pattern generation

A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.

[1]  Eric Lindbloom,et al.  Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test , 1983, IBM J. Res. Dev..

[2]  B. Courtois,et al.  GENERATION OF VECTOR PATTERNS THROUGH RESEEDING OF , 1992 .

[3]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[4]  Hans-Joachim Wunderlich,et al.  TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control , 1991 .

[5]  Kewal K. Saluja,et al.  Test Scheduling and Control for VLSI Built-In Self-Test , 1988, IEEE Trans. Computers.

[6]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[7]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[8]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[9]  Nur A. Touba,et al.  Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[10]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[11]  Arnold L. Rosenberg,et al.  Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing , 1983, IEEE Transactions on Computers.

[12]  Hans-Joachim Wunderlich,et al.  Configuring flip-flops to BIST registers , 1994, Proceedings., International Test Conference.

[13]  S. Hellebrand,et al.  Pattern generation for a deterministic BIST scheme , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[14]  Edward J. McCluskey,et al.  Synthesizing for scan dependence in built-in self-testable designs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[15]  Clay S. Gloster,et al.  Hardware-based weighted random pattern generation for boundary scan , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[16]  S. B. Akers,et al.  On the use of linear sums in exhaustive testing , 1987 .

[17]  Janusz Rajski,et al.  Generation of correlated random patterns for the complete testing of synthesized multi-level circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[18]  Hans-Joachim Wunderlich,et al.  Mixed-Mode BIST Using Embedded Processors , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[19]  O. F. Haberl,et al.  The synthesis of self-test control logic , 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.

[20]  Hans-Joachim Wunderlich,et al.  Error masking in self-testable circuits , 1990, Proceedings. International Test Conference 1990.

[21]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[22]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .

[23]  Johnny J. LeBlanc,et al.  LOCST: A Built-In Self-Test Technique , 1984, IEEE Design & Test of Computers.

[24]  Rudolf Lide,et al.  Finite fields , 1983 .

[25]  Hans-Joachim Wunderlich,et al.  Self test using unequiprobable random patterns , 1987 .

[26]  Paul H. Bardell,et al.  Parallel Pseudorandom Sequences for Built-In Test , 1984, ITC.

[27]  H. Wunderlich,et al.  Bit-flipping BIST , 1996, ICCAD 1996.

[28]  Hans-Joachim Wunderlich,et al.  Generating pseudo-exhaustive vectors for external testing , 1990, Proceedings. International Test Conference 1990.

[29]  Thomas Kropf,et al.  HIST: A hierarchical self test methodology for chips, boards, and systems , 1995, J. Electron. Test..