Patterning Aware Design Optimization of Selective Etching in N5 and Beyond

The aggressive scaling towards N5 causes the difficulty in controlling process variations for line and block (cut) printing, while the margin for edge placement errors (EPE) is decreasing. Selective etching, implemented by self-aligned multiple patterning with alternating materials, introduces better EPE margins with self-aligned blocks (SAB). In this paper, we propose a systematic study on design space for SAB with various options of design rules. We also develop a post SAB optimization framework to evaluate the impacts of different rules. Based on the experiments on 6-track industrial benchmarks, we explore possible options for closure of current physical design flow.

[1]  Diederik Verkest,et al.  Metal stack optimization for low-power and high-density for N7-N5 , 2016, SPIE Advanced Lithography.

[2]  Evangeline F. Y. Young,et al.  Incorporating cut redistribution with mask assignment to enable 1D gridded design , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Diederik Verkest,et al.  Impact of a SADP flow on the design and process for N10/N7 metal layers , 2015, Advanced Lithography.

[4]  Yijian Chen,et al.  A paradigm shift in patterning foundation from frequency multiplication to edge-placement accuracy: a novel processing solution by selective etching and alternating-material self-aligned multiple patterning , 2016, SPIE Advanced Lithography.

[5]  Chris C. N. Chu,et al.  Throughput optimization for SADP and e-beam based manufacturing of 1D layout , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  Yuelin Du,et al.  Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design , 2012, 17th Asia and South Pacific Design Automation Conference.

[7]  Andrew B. Kahng,et al.  ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology , 2015, SPIE Photomask Technology.

[8]  Jun Zhou,et al.  Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processes , 2016, SPIE Advanced Lithography.

[9]  Vipin Kumar,et al.  A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs , 1998, SIAM J. Sci. Comput..

[10]  Lars W. Liebmann,et al.  The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme , 2015, Advanced Lithography.

[11]  Diederik Verkest,et al.  Maintaining Moore’s law: enabling cost-friendly dimensional scaling , 2015, Advanced Lithography.

[12]  Diederik Verkest,et al.  Standard cell design in N7: EUV vs. immersion , 2015, Advanced Lithography.

[13]  Lei Yuan,et al.  Overcoming scaling barriers through design technology CoOptimization , 2016, 2016 IEEE Symposium on VLSI Technology.