论文信息 - A 90-μW 16 bit 20 KHz-BW feedforward double-sampled sigma-delta modulator in 0.18 CMOS

A 90-μW 16 bit 20 KHz-BW feedforward double-sampled sigma-delta modulator in 0.18 CMOS

This paper presents a low power, area-efficient feedforward double-sampling sigma delta modulator. A novel double sampled structure that combines two techniques was proposed. The DAC capacitor reset technique is used to eliminate the noise folding caused by the mis match between two sampling branches; a direct summation scheme obviates analog adder in the front of the quantizer, which greatly relaxes the timing constraints in the feedforward path. The modulator is implemented in the SMIC 0.18um technology; the simulation results show the modulator provides 102.5dB SNDR over a 20-KHz signal bandwidth. The power consumption of modulator is 90μW under 1.5V power supply.

Long Xu | Hai-gang Yang | Fei Liu

[1] Pavan Kumar Hanumolu,et al. A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer , 2010, IEEE Custom Integrated Circuits Conference 2010.

[2] Stephen H. Lewis,et al. A second-order double-sampled delta-sigma modulator using individual-level averaging , 1997 .

[3] G. Nicollini,et al. Low-voltage double-sampled /spl Sigma//spl Delta/ converters , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[4] Jose Silva-Martinez,et al. Enhancing general performance of folded cascode amplifier by recycling current , 2007 .

[5] Yong Lian,et al. A 1.2-V 2.7-mW 160MHz continuous-time delta-sigma modulator with input-feedforward structure , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[6] Sergio Pernici,et al. Low-voltage double-sampled ΣΔ converters , 1997 .

[7] Stephen H. Lewis,et al. A second-order double-sampled delta-sigma modulator using additive-error switching , 1996 .