A LDPC Decoder Based on Efficient Memory Design in DVB-S2 Standard

In this paper, a LDPC decoder based on efficient variable node memory structure design is proposed to reduce the time cost of accessing data in the pipeline. Firstly, we prepare the table corresponding to the variable node memory structure. So we can access the data only by reading the table. On this basis, the check node update order is adjusted to avoid performance loss caused by the conflict between adjacent ones. This method is applicable to all code rates, and does not bring loss of decoding performance. It greatly increase the throughput of the decoder, with an affordable resource consumption. Based on the proposed architectures, a high speed LDPC decoder is implemented on Stratix V 5SGXEA7N2F45C2N FPGA, achieves a throughput of 2.05 Gbps for DVB-S2 code rate 2/3 and a throughput of 2.73 Gbps for rate 4/5.

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