Over the past couple of decades, trends in both microarchitecture and underlying semiconductor technology have significantly reduced microprocessor clock periods. These trends have significantly increased relative main-memory latencies as measured in processor clock cycles. To avoid large performance losses caused by long memory access delays, microprocessors rely heavily on a hierarchy of cache memories. But cache memories are not always effective, either because they are not large enough to hold a program's working set, or because memory access patterns don't exhibit behavior that matches a cache memory's demand-driven, line-structured organization. To partially overcome cache memories' limitations, we organize data cache prefetch information in a new way, a GHB (global history buffer) supports existing prefetch algorithms more effectively than conventional prefetch tables. It reduces stale table data, improving accuracy and reducing memory traffic. It contains a more complete picture of cache miss history and is smaller than conventional tables.
[1]
Anand Sivasubramaniam,et al.
Going the distance for TLB prefetching: an application-driven study
,
2002,
ISCA.
[2]
Olivier Temam,et al.
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
,
2004,
37th International Symposium on Microarchitecture (MICRO-37'04).
[3]
Alan Jay Smith,et al.
Sequential Program Prefetching in Memory Hierarchies
,
1978,
Computer.
[4]
Josep Torrellas,et al.
Using a user-level memory thread for correlation prefetching
,
2002,
ISCA.
[5]
Jean-Loup Baer,et al.
Effective Hardware Based Data Prefetching for High-Performance Processors
,
1995,
IEEE Trans. Computers.
[6]
Dirk Grunwald,et al.
Prefetching Using Markov Predictors
,
1999,
IEEE Trans. Computers.