Design of Small Area and Low Power Consumption Mask ROM

The compact full custom layout design of a 16-Kb mask-programmable CMOS ROM with low power dissipation is introduced in this paper. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 PJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 mum 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, not only the layout design can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.

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