Hardware Cache Coherence Protocol

AbstractThis article describes a new hardware cache coherence protocol based on sequential consistency. The protocol uses the directory scheme and invalidation strategy. Two circuits ensure the management of this protocol, one at the processor level and another at each memory bench level, which is organized in serial multiport memory modules.

[1]  Anoop Gupta,et al.  TEMPORAL, PROCESSOR, AND SPATIAL LOCALITY IN MULTIPROCESSOR MEMORY REFERENCES , 1990 .

[2]  David J. Lilja,et al.  Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons , 1993, CSUR.

[3]  Mark D. Hill,et al.  Retrospective: weak ordering—a new definition , 1998, ISCA '98.

[4]  Calvin K. Tang.  Cache system design in the tightly coupled multiprocessor system , 1976, AFIPS '76.

[5]  Anoop Gupta,et al.  Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, ISCA '90.

[6]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[7]  Anant Agarwal,et al.  Directory-based cache coherence in large-scale multiprocessors , 1990, Computer.

[8]  Donald Yeung,et al.  The MIT Alewife Machine , 1999, Proc. IEEE.

[9]  Donald Yeung,et al.  Sparcle: an evolutionary processor design for large-scale multiprocessors , 1993, IEEE Micro.

[10]  Sarita V. Adve,et al.  Recent advances in memory consistency models for hardware shared memory systems , 1999, Proc. IEEE.

[11]  Willy Zwaenepoel,et al.  Implementation and performance of Munin , 1991, SOSP '91.

[12]  Donald Yeung,et al.  The MIT Alewife machine: architecture and performance , 1995, ISCA '98.

[13]  Liviu Iftode,et al.  Scope consistency: a bridge between release consistency and entry consistency , 1996, SPAA '96.

[14]  James K. Archibald,et al.  Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.

[15]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[16]  Alan Jay Smith,et al.  Cache Memories , 1982, CSUR.

[17]  Weisong Shi,et al.  An interaction of coherence protocols and memory consistency models in DSM systems , 1997, OPSR.

[18]  Anant Agarwal,et al.  Closing the window of vulnerability in multiphase memory transactions , 1992, ASPLOS V.

[19]  Zoran Salcic,et al.  Digital Systems Design and Prototyping Using Field Programmable Logic , 1997 .