An FPGA design of low power LDPC decoder for high-speed wireless LAN

This paper proposes three kinds of simplified complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. Second, an early detection method for reducing the computational complexity is proposed. Finally, in order to support the high-speed systems, we implemented LDPC decoder using three algorithms by N=648, R=1/2. And the decoder runs at a clock speed of 10ns. Therefore we implemented the LDPC decoder with the decoding speed of 110Mbps.