An hardware efficient deblocking filter for H.264/AVC

This work presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with a gate count of 9.16 K when synthesized from Verilog RTL design by using UMC 0.18 /spl mu/m CMOS technology. When clocked at 82.58 MHz, our design can easily support real-time deblocking of 2K /spl times/ 1K @ 30 Hz video application; this high performance can meet high resolution real-time application requirement.