Verilog Implementation of UART with Status Register

In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback and emerges as a effective candidate in many applications for long distance communication as it reduces the signal distortion because of its simple structure. This paper focuses on the Verilog HDL implementation of UART with status register which supports asynchronous serial communication. This paper presents the architecture of UART which indicates, during reception of data, parity error, framing error, overrun error and break error using status register. In the proposed method for error correction hamming code is used. By using the hamming code, single bit error can be detected and corrected. The whole design is functionally verified using Xilinx ISE Simulator. In this paper we propose a technique for software implementation of an UART with the goal of getting a customizable UART-core which can be used as a module in implementing a bigger system irrespective of one's choice of implementation platform. The simulation results as well as the test results are seen to be satisfactory.

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