A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS

A second generation, contrast sensitive silicon retina is reported in this paper. The architecture and organization is inspired by the outer plexiform processing in the vertebrate retina. Current-mode subthreshold MOS design techniques are employed to obtain high performance and energetic efficiency. The system has been fabricated with 230/spl times/210 pixels on a 1/spl times/1 cm die in a 1.2 /spl mu/m n-well double metal, double poly, digital oriented CMOS technology. The chip incorporates 590,000 transistors, 48,000 pixels, operating in subthreshold/transition region with power dissipation of 50 mW when powered from a 5 V power supply. The pixel has a frequency response of 100 kHz.