Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology. The two types of chips are using 20 μm diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module. Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.

[1]  W. Marsden.  I and J , 2012 .

[2]  Ashok V. Krishnamoorthy,et al.  Integration, processing and performance of low power thermally tunable CMOS-SOI WDM resonators , 2012 .

[3]  D. B. Buchholz,et al.  High-speed optoelectronic VLSI switching chip with >4000 optical I/O based on flip-chip bonding of MQW modulators and detectors to silicon CMOS , 1996 .

[4]  W. S. Hobson,et al.  Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits , 1999, IEEE Photonics Technology Letters.

[5]  L.A. Coldren.  Silicon photonics for next generation computing systems , 2008, 2008 34th European Conference on Optical Communication.

[6]  Ashok V. Krishnamoorthy,et al.  Hybrid integration of silicon nanophotonics with 40nm-CMOS VLSI drivers and receivers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[7]  H. Thacker,et al.  Exploiting CMOS Manufacturing to Reduce Tuning Requirements for Resonant Optical Devices , 2011, IEEE Photonics Journal.

[8]  R. Ho,et al.  Integration and Packaging of a Macrochip With Silicon Nanophotonic Links , 2011, IEEE Journal of Selected Topics in Quantum Electronics.

[9]  Ashok V. Krishnamoorthy,et al.  Computer Systems Based on Silicon Photonic Interconnects A proposed supercomputer-on-a-chip with optical interconnections between processing elements will require development of new lower-energy optical components and new circuit architectures that match electrical datapaths to complementary optical , 2009 .

[10]  Xuezhe Zheng,et al.  Highly-efficient thermally-tuned resonant optical filters. , 2010, Optics express.

[11]  J. Cunningham,et al.  GaAs 850 nm modulators solder-bonded to silicon , 1993, IEEE Photonics Technology Letters.

[12]  R. Stephenson.  A and V , 1962, The British journal of ophthalmology.

[13]  E. Alon,et al.  A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems. , 2010, Optics express.

[14]  Ashok V. Krishnamoorthy,et al.  Optoelectronic-VLSI: photonics integrated with VLSI circuits , 1998 .

[15]  D. Ahn,et al.  Electronic-photonic integrated circuits on the CMOS platform , 2006, SPIE OPTO.

[16]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[17]  S. G. Kim,et al.  Mach-Zehnder silicon modulator on bulk silicon substrate; toward DRAM optical interface , 2010, 7th IEEE International Conference on Group IV Photonics.

[18]  James G. Mitchell,et al.  Flip-chip integrated silicon photonic bridge chips for sub-picojoule per bit optical links , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).