An automated development framework for a RISC processor with reconfigurable instruction set extensions

By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compiler of the processor to take into account reconfigurable aspects. In this paper, a development framework for a RISC processor with reconfigurable instruction set extensions is presented. The framework is fully automated, hiding all reconfigurable related issues from the user and can be used for both program and fine-tune the architecture at design time. We demonstrate the above issues using a set of benchmarks. Experimental results show an x2.9 average speedup in addition to potential energy reduction

[1]  Luciano Lavagno,et al.  Software development for high-performance, reconfigurable, embedded multimedia systems , 2005, IEEE Design & Test of Computers.

[2]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[3]  Maya Gokhale,et al.  NAPA C: compiling for a hybrid RISC/FPGA architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[4]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[5]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[6]  George Theodoridis,et al.  A RISC architecture extended by an efficient tightly coupled reconfigurable unit , 2006 .

[7]  Prithviraj Banerjee,et al.  A C compiler for a processor with a reconfigurable functional unit , 2000, FPGA '00.

[8]  Cesare Alippi,et al.  A DAG-Based Design Approach for Reconfigurable VLIW Processors , 1999, DATE.

[9]  Stamatis Vassiliadis,et al.  The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.

[10]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[11]  Spiridon Nikolaidis,et al.  Automated instruction-set extension of embedded processors with application to MPEG-4 video encoding , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[12]  Rudy Lauwereins,et al.  Reconfigurable Instruction Set Processors from a Hardware/Software Perspective , 2002, IEEE Trans. Software Eng..