0.94ps-rms-jitter 0.016mm/sup 2/ 2.5GHz multi-phase generator PLL with 360/spl deg/ digitally programmable phase shift for 10Gb/s serial links

A PLL generates 8 equidistant clock phases whose timing with respect to a reference clock can be simultaneously shifted in 3ps steps by a digital value. Each VCO phase is fed to a dedicated phase detector and the weighted detector outputs are summed. Fabricated in 90nm SOI-CMOS technology, the PLL has a jitter of 0.94ps/sub rms/ at 2.5GHz and consumes 20mW from a 0.9V supply.

[1]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[2]  J. W. Scott,et al.  z-domain model for discrete-time PLL's , 1988 .

[3]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[4]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997 .

[5]  P. Larsson,et al.  A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability , 1999, IEEE J. Solid State Circuits.

[6]  Lizhong Sun,et al.  A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator , 2001, IEEE J. Solid State Circuits.

[7]  W.J. Dally,et al.  An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[8]  Chih-Kong Ken Yang,et al.  Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[9]  Jaeha Kim,et al.  Adaptive supply serial links with sub-1 V operation and per-pin clock recovery , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[10]  S. Narasimha,et al.  A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[11]  J. Lee,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Mark Horowitz,et al.  A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs , 2003 .

[13]  M. Mansuri,et al.  A 27-mW 3.6-Gb/s I/O transceiver , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[14]  Behzad Razavi,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .

[15]  R. Senthinathan,et al.  A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os , 2004, IEEE Journal of Solid-State Circuits.

[16]  A. Maxim.  Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation , 2005, IEEE Journal of Solid-State Circuits.