A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components

[1]  Eitake Ibaragi,et al.  A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Takaya Yamamoto,et al.  A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver , 2013, IEEE Journal of Solid-State Circuits.

[3]  Yung-Hui Chung,et al.  A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[4]  Un-Ku Moon,et al.  A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC , 2013, 2013 Symposium on VLSI Circuits.

[5]  Tai-Cheng Lee,et al.  A 0.02-mm$^{2}$ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[6]  Un-Ku Moon,et al.  A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information , 2014, IEEE Journal of Solid-State Circuits.

[7]  Koichi Hamashita,et al.  Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[9]  Takashi Morie,et al.  A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[10]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[11]  Kazuyuki Aihara,et al.  Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm , 2014, IEICE Trans. Electron..

[12]  Kazuyuki Aihara,et al.  Robust Cyclic ADC Architecture Based on β-Expansion , 2013, IEICE Trans. Electron..

[13]  Jae-Won Nam,et al.  A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[14]  Kazuyuki Aihara,et al.  An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[15]  Boris Murmann,et al.  A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end , 2013, 2013 Symposium on VLSI Circuits.