Mobile Display Drivers

Figure 17.9.4 shows a schematic of the current-mode S/H. During the sampling mode (SW = 1), the input current flows to node X and the charge corresponding to it is trapped on sampling capacitor CH. The maximum sampling speed of the S/H is determined by the settling time constant of node X. In the S/H, a negativefeedback loop through M3-M8-M2-M1-M11 is applied during the sampling mode; as a result, node X is virtually grounded to Vb1. This allows the sampling speed of the S/H to be enhanced significantly. In addition, the Miller compensation capacitor CH works as a sampling capacitor while guaranteeing a stable feedback loop. During the hold mode (SW = 0), the feedback loop is broken by turning off the switch, MSW, leaving the S/H as a current source. The major limitation of the linearity of the S/H is due to charge injection when the MSW turns off. In the S/H, mitigation of the charge injection is accomplished by two methods: a dummy switch and a boost of the sampling capacitance CH by the Miller enhancement method. Additionally, the drain and source voltages of the MSW always remain with the constant voltage Vb1 regardless of the input current level due to the feedback loop. Therefore, it is possible to achieve signal-independent charge injection and improve the linearity of the current-mode S/H significantly. Lastly, the output impedance of the S/H during the hold mode is boosted by utilizing a regulated cascode circuit (M9-M14), which serves as an ideal current source. On the right hand side of Fig. 17.9.4, the linearity simulation result of the S/H at a sampling rate of 2.5MS/s is shown. The maximum error current is 0.1LSB (1nA) in 9b resolution, which is sufficient for the DAC. A prototype of the 9b SI DAC was fabricated in a 0.35μm 3.3V CMOS process. Figure 17.9.5 shows the measured INL and DNL of the DAC. The maximum INL and DNL with path swapping (without path swapping) are 1.6LSB (3.8LSB) and 0.8LSB (2LSB), respectively. The deviation of current output (DCO) was also measured for 512 gray scales in 8 channels, and a maximum inter-channel DCO of 15nA was achieved. Figure 17.9.6 summarizes the measured performance of the prototype DAC and compares it with previous works. The chip size per channel DAC is 0.014mm 2 in this design, which is much smaller than those reported recently. The D/A conversion speed is 1μs/b with a static current of 10μA. A die micrograph is shown in Fig. 17.9.7.

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[2]  A. Nathan,et al.  Driving schemes for a-Si and LTPS AMOLED displays , 2005, Journal of Display Technology.