论文信息 - Background digital error correction technique for pipelined analog-digital converters

Background digital error correction technique for pipelined analog-digital converters

This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm has been shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework.

Jan Van der Spiegel | K. Nagaraj | Sameer R. Sonkusale

[1] David A. Johns,et al. Comparison of DC offset effects in four LMS adaptive algorithms , 1995 .

[2] Un-Ku Moon,et al. Background digital calibration techniques for pipelined ADCs , 1997 .

[3] A. Karanicolas,et al. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[4] Hae-Seung Lee. A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC , 1994 .

[5] Bruce A. Wooley,et al. A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter , 1998 .

[6] Bang-Sup Song,et al. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[7] S. Haykin,et al. Adaptive Filter Theory , 1986 .

[8] Sameer Sonkusale,et al. True background calibration technique for pipelined ADC , 2000 .

[9] Un-Ku Moon,et al. Digital Calibration Techniques for Pipelined ADC ’ s , 1997 .

[10] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.