A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-/spl mu/m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3/spl times/ oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of /spl sim/3/spl times/3 mm/sup 2/.

[1]  A. Yukawa,et al.  A CMOS 8-Bit High-Speed A/D Converter IC , 1984, IEEE Journal of Solid-State Circuits.

[2]  Victor E. Lee,et al.  A 500-megabyte/s data-rate 4.5 M DRAM , 1993 .

[3]  M. Horowitz,et al.  Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  Deog-Kyoon Jeong,et al.  An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[5]  T. Frank,et al.  Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter , 1995 .