论文信息 - Yield loss forecasting in the early phases of the VLSI design process

Yield loss forecasting in the early phases of the VLSI design process

This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.

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