Investigation of gray-scale technology for large area 3D silicon MEMS structures

Micromachining arbitrary 3D silicon structures for micro-electromechanical systems can be accomplished using gray-scale lithography along with dry anisotropic etching. In this study we have investigated two important design limitations for gray-scale lithography: the minimum usable pixel size and maximum usable pitch size. Together with the resolution of the projection lithography system and the spot size used to write the optical mask, the maximum range of usable gray levels can be determined for developing 3D large area silicon structures. An approximation of the minimum pixel size is shown and experimentally confirmed. Below this minimum, gray levels will be developed away due to an excessive amount of intensity passing through the optical mask. Additionally, oscillations in the intensity are investigated by the use of large pitch sizes on the optical mask. It was found that these oscillations cause holes in the photoresist spaced corresponding to the pitch used on the gray-scale mask and penetrate the thickness of the photoresist for thin gray levels. From the holes in the photoresist, significant surface roughness results when used as a nested mask in reactive ion etching, and the very thin gray levels are lost.

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