An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA

In this work, an autonomous power and clock gating technique for finite state machine (FSM) is being implemented in a programmable TILE. A TILE is the basic building block of a field-programmable gate array (FPGA), which is repeated over and again to form the entire FPGA structure. We have designed and simulated a transistor-level SRAM-based TILE architecture in CADENCE tool, using a technology of 45 nm. The transistor-level design of the TILE provides the scope for in-depth and elaborate analyses of the architecture. We have implemented a basic FSM circuit in the TILE and then introduced a dynamic power and clock gating technique. The logic of gating is based on the knowledge of self-loops in an FSM and works at a fine level of granularity. Our approach has successfully resulted in reducing approximately 19% of the total power dissipation of the TILE architecture with a minimal increase in delay. The area overhead in our approach is only a mere 3.7%.