On Error Correction In Macro-based Circuits

We consider the problem of correcting errors in a macro-based circuit. Our formulation of the problem allows the correction of errors that arise both in the context of design error correction, before the circuit is realized, and in the context where a physical circuit needs to be corrected. Two error classes are defined, namely, component errors and line errors. Both single and multiple errors are considered. Accurate correction procedures are given for single errors. Heuristics are given for correcting multiple errors. Experimental results are given to demonstrate the correction procedures presented.

[1]  Liaw Heh-Tyan,et al.  Efficient automatic diagnosis of digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[2]  Hiroshi Takahashi,et al.  Multiple fault diagnosis by sensitizing input pairs , 1995, IEEE Design & Test of Computers.

[3]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[4]  Ulf Schlichtmann,et al.  Characterization of Boolean functions for rapid matching in EPGA technology mapping , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[5]  K. A. Tamura,et al.  Locating Functional Errors in Logic Circuits , 1989, 26th ACM/IEEE Design Automation Conference.

[6]  Irith Pomeranz,et al.  Testability considerations in technology mapping , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[7]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[8]  Magdy S. Abadir,et al.  Logic design verification via test generation , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Kenneth R. Bowden,et al.  The Modern Fault Dictionary , 1985, ITC.

[10]  Resve A. Saleh,et al.  Exact evaluation of diagnostic test resolution , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  S.D. Millman,et al.  Diagnosing CMOS bridging faults with stuck-at fault dictionaries , 1990, Proceedings. International Test Conference 1990.

[12]  David Hung-Chang Du,et al.  Testability considerations , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[13]  Sy-Yen Kuo,et al.  Locating logic design errors via test generation and don't-care propagation , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[14]  Masahiro Fujita,et al.  Rectification method for lookup-table type FPGA's , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[15]  Edward J. McCluskey,et al.  Test and Diagnosis Procedure for Digital Networks , 1971, Computer.

[16]  Ibrahim N. Hajj,et al.  ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits , 1992, Proceedings International Test Conference 1992.

[17]  Robert K. Brayton,et al.  A Redesign Technique For Combinational Circuits Based On Gate Recomections , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[18]  Paolo Prinetto,et al.  Diagnosis oriented test pattern generation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[19]  Irith Pomeranz,et al.  On correction of multiple design errors , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Robert C. Aitken,et al.  Fault Location with Current Monitoring , 1991, 1991, Proceedings. International Test Conference.

[21]  Masahiro Tomita,et al.  An algorithm for locating logic design errors , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[22]  Olivier Coudert,et al.  Automating the diagnosis and the rectification of design errors with PRIAM , 1989, ICCAD 1989.

[23]  Elizabeth M. Rudnick,et al.  Diagnostic Fault Simulation of Sequential Circuits , 1992, Proceedings International Test Conference 1992.

[24]  Melvin A. Breuer,et al.  Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis , 1980, IEEE Transactions on Computers.

[25]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[26]  Janusz Rajski,et al.  A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..