Analytical performance analysis and modeling of superscalar and multi-threaded processors

viii SAMENVATTING demonstreren we met een studie van de prestatie-impact van verschil-lende compileroptimalisaties. We hebben ook de prestatietellerarchitectuur uitgebreid naar meer-dradige processors (SMT processors). Het belangrijkste probleem in meerdradige processors is de onderlinge prestatiebe¨ınvloeding tussen de draden, wat het moeilijk maakt om de prestatie van de individuele draden te isoleren. Daarom ontwikkelden we een mechanisme dat in staat is de cycle component stacks van elk van de individuele draden te reconstrueren alsof ze ge¨ısoleerd op eenééndradige processor zou-den uitvoeren. Daardoor kan het de voortgang van elk van de draden nauwkeurig schatten, wat nuttig is voor systeemsoftware of-hardware om in een bepaalde dienstverleningskwaliteit (bv. prestatiegarantie) te voorzien op meerdradige processors. Summary Due to its complexity, analyzing the performance of a modern super-scalar processor is a challenging task. The processor can execute multiple instructions per cycle, and the instructions execute possibly out-of-order. In addition, various miss events can happen at different stages in the processor pipeline: the fetching of instructions can stall due to instruction cache misses, branch mispredictions cause the fetching of wrong-path instructions, which will eventually be flushed, and data cache misses can drastically delay the execution of memory instructions. Furthermore, miss event handling can be overlapped with instruction execution and/or the handling of other miss events. Multi-threaded processors (e.g., simultaneous multithreading (SMT) processors) are even more difficult to analyze, since the concurrently executing threads are closely interlaced and have an impact on each other's performance. As such, it is difficult to get an intuitive understanding of the performance of a program executing on a contemporary processor, and get insight into how big the performance impact is of the various miss events that can occur within the processor. Therefore, performance evaluation in an experimental context has shifted towards simulation. Simulation has the advantage that it is very flexible and that its overall performance estimations are very accurate. It is however very time-consuming, simulating a few seconds of real execution time can take hours or days, even with the fastest simulators running on today's fastest computers. It also provides little insight into the factors that determine overall performance. The lack of insight also makes accurate on-line performance monitoring more difficult. Hardware performance counters can measure various events that have an impact on performance, but they do not quantify the contribution of these events to overall performance. There-x SUMMARY fore, the insight they provide into the performance of a program executing on …

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