Automatic Layout of Switch-Level Designs

Most VLSI layout styles in use today fall into a few broad categories. These include dedicated site styles such as gate arrays and sea-of-gates, prepared library styles such as standard cells, gate-matrix [Lope80], and full-custom design. Each of these has advantages and disadvantages in terms of performance versus design time, with gate arrays generally being the quickest to obtain and full-custom design being the highest performance. The Silicon Converter system is a tool designed to produce compact and electrically high-performing MOS layouts. It operates somewhere in the range between standard cells and traditional full-custom design. Like standard cells, it can produce a layout with almost no designer intervention. Like traditional full-custom design styles, it can handle arbitrary transistor-level circuit specifications and is not limited to those found in a library. It can take advantage of regular structures if present, or dedicated floorplans if they are available. Naturally, the layout for a given function may not be as tight as the best special purpose generator (e.g. PLA, ROM, RAM, etc.), but it can be highly effective for a wide range of design situations.